![\"eesc](\"http:\/\/portal.eesc.usp.br\/imgs\/jaguar\/eesc_crob_logo_site.JPG\"){kind=logo}
<\/a>Confira um breve resumo dos temas dos projetos, que s\u00e3o financiados pela Universidade de Sydney (Austr\u00e1lia) e pela FAPESP, respectivamente.<\/p>\n<\/p>\n
T\u00edtulo<\/strong>: Projetos em Vis\u00e3o Computacional e Aprendizagem de M\u00e1quinas<\/em> Palestrante<\/strong>: Vitor Campanholo Guizilini (Universidade de Sydney)<\/p>\n Resumo<\/strong>: a apresenta\u00e7\u00e3o ser\u00e1 uma introdu\u00e7\u00e3o a alguns dos projetos que a Universidade de Sydney tem em andamento, visando a poss\u00edveis colabora\u00e7\u00f5es com grupos de pesquisa brasileiros. Ser\u00e3o abordados os seguintes t\u00f3picos: SLAM Visual, Reconstru\u00e7\u00e3o 3D de ambientes, Fus\u00e3o de Dados, Drones na Agricultura e Sistemas de Sa\u00fade Inteligentes.<\/p>\n <\/p>\n T\u00edtulo<\/strong>: Analysis of FPGA based Systolic array Robust Markovian Jump Kalman Filter for Attitude Estimation<\/em> Palestrante:<\/strong> Mundla Narasimhappa (University of Hyderabad, \u00cdndia)<\/p>\n Resumo em ingl\u00eas<\/strong>: “My outline of the talk can be divided into two sections. In the first section, brief cover my Ph.D. work. In the second section, the development of systolic array architecture based robust recursive Markovian jump Kalman filter (RRMJKF) and its real time hardware computation using Field programmable gate array (FPGA). The main contribution of work is to use FPGA based systolic array RRMJKF for determining the vehicle attitude estimation of AHRS (Attitude and Heading Reference System). In the AHRS, both low cost inertial measurement unit (IMU) and manometer sensor are core components are widely used for providing the attitude information, in terms of quaternion. In general, the quality of sensor depends on an accurate of sensor error models and uses robust filtering. In real time, optimal algorithm implementation is a key issue and guarantee the stability for AHRS vehicles. So that, FPGA is a hardware computation device in real time analysis. To reduce the filter complexity, systolic array architectures are better choice, in which, both pipelining and parallelism operations can be performed. A FPGA based systolic array RRMJKF architecture is proposed based Given rotation algorithm for QR decomposition, which is expressed in linear equations. Finally, the proposed architecture is implemented in Altera Cyclone V SOC board using NIOS II Softcore processor.”<\/p>\n <\/p>\n [+] informa\u00e7\u00e3o<\/p>\n Professor Marco Henrique Terra Departamento de Engenharia El\u00e9trica e de Computa\u00e7\u00e3o da EESC Tel.: (16) 3373-9341 E-mail: terra@sc.usp.br<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"