Centro de Robótica de São Carlos realiza seminários

Confira um breve resumo dos temas dos projetos, que são financiados pela Universidade de Sydney (Austrália) e pela FAPESP, respectivamente.

Título: Projetos em Visão Computacional e Aprendizagem de Máquinas Palestrante: Vitor Campanholo Guizilini (Universidade de Sydney)

Resumo: a apresentação será uma introdução a alguns dos projetos que a Universidade de Sydney tem em andamento, visando a possíveis colaborações com grupos de pesquisa brasileiros. Serão abordados os seguintes tópicos: SLAM Visual, Reconstrução 3D de ambientes, Fusão de Dados, Drones na Agricultura e Sistemas de Saúde Inteligentes.

Título: Analysis of FPGA based Systolic array Robust Markovian Jump Kalman Filter for Attitude Estimation Palestrante: Mundla Narasimhappa (University of Hyderabad, Índia)

Resumo em inglês: "My outline of the talk can be divided into two sections. In the first section, brief cover my Ph.D. work. In the second section, the development of systolic array architecture based robust recursive Markovian jump Kalman filter (RRMJKF) and its real time hardware computation using Field programmable gate array (FPGA). The main contribution of work is to use FPGA based systolic array RRMJKF for determining the vehicle attitude estimation of AHRS (Attitude and Heading Reference System). In the AHRS, both low cost inertial measurement unit (IMU) and manometer sensor are core components are widely used for providing the attitude information, in terms of quaternion. In general, the quality of sensor depends on an accurate of sensor error models and uses robust filtering. In real time, optimal algorithm implementation is a key issue and guarantee the stability for AHRS vehicles. So that, FPGA is a hardware computation device in real time analysis. To reduce the filter complexity, systolic array architectures are better choice, in which, both pipelining and parallelism operations can be performed. A FPGA based systolic array RRMJKF architecture is proposed based Given rotation algorithm for QR decomposition, which is expressed in linear equations. Finally, the proposed architecture is implemented in Altera Cyclone V SOC board using NIOS II Softcore processor."

informação

Professor Marco Henrique Terra Departamento de Engenharia Elétrica e de Computação da EESC Tel.: (16) 3373-9341 E-mail: terra@sc.usp.br